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BELAS Summer School 2018

TTEP Tutorial

Power-Aware Testing in the Era of IoT

Patrick Girard, LIRMM, CNRS, France
Xiaoqing Wen, Kyushu Institute of Technology, Japan

Managing the power consumption of circuits and systems has become one of the most important challenges for the semiconductor industry, especially in the era of IoT. Sophisticated power management techniques, such as voltage scaling, clock gating, power gating, etc., are widely used today to control the power dissipation during the functional operation. Since the application of these techniques has profound implications on manufacturing test, power-aware testing has become indispensable for low-power LSIs and IoT devices. This tutorial provides a comprehensive and practical coverage of power-aware testing, with the following three parts. The first part gives the background and discusses various problems arising from excessive power dissipation during scan testing. The second part provides comprehensive information on structural and algorithmic solutions for alleviating the test-power- related problems. The third part outlines low power design techniques and shows how these low power devices can be tested safely without affecting yield and reliability.

Short Bios:
Patrick Girard:
Received a M.Sc. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research Director at CNRS (French National Center for Scientific Research) and works in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) - France. From 2010 to 2014, he was head of this Microelectronics Department. He is co-Director of the International Associated Laboratory «LAFISI» (French-Italian Research Laboratory on Hardware-Software Integrated Systems) created in 2013 by the CNRS and the University of Montpellier with the Politecnico di Torino, Italy. His research interests include all aspects of digital testing and memory testing, with emphasis on critical constraints such as timing and power. Reliability and approximate computing are also part of his research activities. He has served on numerous conference committees and is the founder and Editor-in- Chief of the ASP Journal of Low Power Electronics (JOLPE). He is also an Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on CAD and the Journal of Electronic Testing – Theory and Applications (JETTA - Springer). He has supervised 35 PhD dissertations and has published 7 books or book chapters, 65 journal papers, and more than 230 conference and symposium papers on these fields. Patrick Girard is a Fellow of IEEE.

Xiaoqing Wen:
Received a B.E. degree from Tsinghua University, China, in 1986, a M.E. degree from Hiroshima University, Japan, in 1990, and a Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was an Assistant Professor at Akita University, Japan. He was a Visiting Researcher at University of Wisconsin, Madison, USA, from October 1995 to March 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served as its CTO until 2003. In 2004, he joined Kyushu Institute of Technology, Japan, where he is currently a Professor and the Chair of the Department of Creative Informatics. He co-founded Dependabale Integrated Systems Reserch Center (DISC) in 2015 and servied as its first Director. He is a Co-Chair of the Technical Activity Committee on Power-Aware Testing under the Test Technology Technical Council (TTTC) of the IEEE Computer Society. He is serving as Associate Editors for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration Systems, and Journal of Electroics Testing: Theory and Aplications. He co-authored and co-edited two books: VLSI Test Principles and Architectures: Design for Testability (Morgan Kaufmann, 2006) and Power-Aware Testing and Test Strategies for Low Power Devices (Springer, 2009). His research interests include design, test, and diagnosis of integrated circuits. He holds 43 U.S. Patents and 14 Japan Patents. He received the 2008 Society Best Paper Award from the Infromation Systmes Society (ISS) of Institute of Electronics, Information and Communication Engineers (IEICE). He is a Fellow of IEEE, a Senior Member of Information Processing Society of Japan (IPSJ), and a member IEICE.



The Organizing Committee, Porto Alegre (Brazil)