21st IEEE Latin-American Test Symposium

Jatiúca (Maceió), Brazil, 30th March - 2nd April 2020

 

NEWS: CORONAVIRUS

 

After carefully analyzing the global situation related to Corona virus (COVID-19), with full attention for the health and safety of all presenters and attendees, the Organizing Committee of the 21st IEEE Latin American Test Symposium (LATS2020) decided that this year’s edition will be replaced by a virtual conference instead of a physical event that was planned in Maceio (Brazil) from March 30th to April 2nd 2020.

 

Information regarding the new schedule and procedures will be sent in the next few days.

 

 

NEWS: PRELIMINARY TECHNICAL PROGRAM AVAILABLE

 

This year we were able to compile a very broad and interesting technical program for you. Please check our  Technical Program section to view the latest information!

 

 

Natural beauty: the "falesias" at Gunga beach

THE 2020 EVENT

 

The IEEE Latin-American Test Symposium (LATS) is a recognized test and fault tolerance techniques forum attended by professionals from all over the world, in particular from Latin-America, to present and discuss various aspects of system, board, and component testing as well as design, manufacturing and in-field considerations with fault tolerance in mind. All presented papers will be submitted to IEEE Xplore Digital Library  and the best papers of its 21st edition will be invited to re-submit to IEEE Design&Test, Journal of Electronic Testing: Theory and Applications (JETTA - Springer), Journal of Low Power Electronics (JOLPE - American Scientific Publishers), and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

 

 

Topics of interest include but are not limited to:

 

- Automatic Test Generation

- Built-In Self-Test

- Defect-Based Test

- Design and Synthesis for Testability

- Design for Electromagnetic Compatibility

- Design for Reliable Embedded Software

- Design Verification / Validation

- Economics of Test

- Fault Analysis and Diagnosis

- Fault Modeling and Simulation

- Fault-Tolerance in HW/SW

 

 

 

 

- Fault-Tolerant Architectures

- Memory Test and Repair

- On-Line Testing

- Process Control & Measurements

- Radiation / Electromagnetic Interference

- Hardening Techniques

- Software Fault-Tolerance

- Software On-Line Testing

- System-on-Chip Test

- Test Resource Partitioning

- Yield Optimization

- Hardware Security

PAPER SUBMISSION INFORMATION

 

On behalf of the organizing committee, we would like to thank all those who already contributed with their submissions. Soon we will have concluded our thorough review process and notify all authors regarding the selection results.

 

For additional information, please contact our Program Co-Chairs:

 

Victor Champac – INAOE, Mexico   Tiago Balen, UFRGS, Brazil

champac@inaoep.mx                       tiago.balen@ufrgs.br

 

 

IMPORTANT DATES

 

Notification of Acceptance:  January 20th, 2020

Camera Ready: February 5th, 2020.

 

 

 

To download the Call for Papers, please click [here].

 

 

 

 

SPONSORS

 

Financial Co-Sponsors:

 

 

 

 

 

 

Technical Co-Sponsors:

 

The Institute of Electrical and                                        Test Technology

Electronics Engineering, Inc.                                         Technical Council